1. Field of the Invention
The present invention relates to a semiconductor device including a capacitor construction consisting of a lower electrode, an upper electrode and a dielectric film interposed therebetween and a fabricating method of such a semiconductor device.
2. Description of the Related Art
Conventionally, there are known flash memories and ferro-electric random access memories (FeRAMs) as nonvolatile memories which do not erase stored information even when the power supply is turned off.
A flash memory includes a floating gate embedded in the gate insulating film of an insulated gate field effect transistor (IGFET) and stores information by accumulating, at the floating gate, electric charge indicative of information to be stored. In order to write and erase information, it is necessary to pass tunnel currents through the insulating film, thus requiring relatively high voltages.
An FeRAM stores information utilizing the hysteresis characteristic of a ferroelectric. A ferroelectric capacitor construction including a ferroelectric film interposed between a pair of electrodes induces polarization according to the voltage applied between the electrodes and also has spontaneous polarization even when the applied voltage is removed. When the polarity of the applied voltage is reversed, the polarity of spontaneous polarization is also reversed. By detecting the spontaneous polarization, information can be read out therefrom. An FeRAM can operate with a lower voltage as compared with a flash memory, thereby having an advantage of being capable of rapidly writing with low electric power. There have been studied SOCs (System On Chip) utilizing such FeRAMs in combination with conventional logic techniques, for applications such as IC cards.    [Patent Document 1] Japanese Patent Application Laid-open No. 2004-303993    [Patent Document 2] Japanese Patent Application Laid-open No. Hei 10-12617
An FeRAM is configured to have a plurality of intricately-laminated layers including transistor constructions and a first insulating film covering them, capacitor constructions and a protective film covering them for suppressing degradations in the characteristics of the capacitor constructions, a second insulating film, additionally multi-layer wirings thereon and an insulating film covering them, etc. Therefore, it is difficult to form connecting holes for establishing electric contact with lower layers to be desired shapes. For example, there is such problem that connecting holes are formed to be shapes having narrowed bottom portions, thus preventing the establishment of reliable electric connections.
Therefore, Patent Document 1 discloses an FeRAM configuration which is fabricated by previously forming openings in a protective film directly covering capacitor constructions for suppressing degradations in the characteristics thereof at the portions corresponding to the portions of connecting holes, and forming respective layers thereon, thus requiring no etching of the protective film when forming the connecting holes extending to the source/drain.
However, when the technique of Patent Document 1 is employed, openings are formed in the protective film provided for suppressing degradations in the characteristics, which will necessarily degrade the blocking function of the protective film against hydrogen or process damages, making it difficult to sufficiently suppress degradations in the characteristics of the capacitor constructions.